Enhanced switched capacitor filter (scf) compensation in dc-dc converters

ABSTRACT

A system, DC-DC converter, and compensation method and circuit for a DC-DC converter are disclosed. For example, a compensation circuit for a DC-DC converter is disclosed. The compensation circuit includes an integrator circuit configured to receive and integrate a first voltage signal, a differential difference amplifier circuit coupled to the integrator circuit and configured to generate a first filter transfer function associated with the integrated first voltage signal, and a switched capacitor filter circuit coupled to the differential difference amplifier circuit and configured to generate a second filter transfer function, wherein the differential difference amplifier is further configured to output a second voltage signal responsive to the first filter transfer function and the second filter transfer function. In one implementation, the compensation circuit is a type-III switched capacitor filter (SCF) compensation circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Provisional Patent Application Ser.No. 62/205,230 entitled “ENHANCED SWITCHED CAPACITOR FILTER (SCF)COMPENSATION IN DC-DC CONVERTERS,” filed on Aug. 14, 2015, and to U.S.Provisional Patent Application Ser. No. 62/253,644 entitled “ENHANCEDSWITCHED CAPACITOR FILTER (SCF) COMPENSATION IN DC-DC CONVERTERS,” filedon Nov. 10, 2015, both of which are incorporated herein by reference.This application hereby claims to the benefit of U.S. Provisional PatentApplication Ser. No. 62/205,230 and 62/253,644.

BRIEF DESCRIPTION OF THE DRAWINGS

Understanding that the drawings depict only exemplary embodiments andare not therefore to be considered limiting in scope, the exemplaryembodiments will be described with additional specificity and detailthrough the use of the accompanying drawings.

FIG. 1 depicts a schematic circuit diagram of a switched capacitorfilter (SCF) compensation circuit that can be utilized to implement oneexemplary embodiment of the present invention.

FIG. 2 depicts a schematic circuit diagram of a SCF compensation circuitthat can be utilized to implement a second exemplary embodiment of thepresent invention.

FIG. 3 depicts a flow diagram of a method that can be utilized toimplement Type-III SCF compensation for a DC-DC converter, in accordancewith one exemplary embodiment of the present invention.

FIG. 4 depicts a schematic circuit diagram of a DC-DC converter that canbe utilized to implement Type-III SCF compensation, in accordance withone exemplary embodiment of the present invention.

FIG. 5 depicts a schematic block diagram of an electronic system thatcan be utilized to implement one exemplary embodiment of the presentinvention.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which are shown byway of specific illustrative embodiments. However, it is to beunderstood that other embodiments may be utilized and that logical,mechanical, and electrical changes may be made. Furthermore, the methodpresented in the drawing figures and the specification is not to beconstrued as limiting the order in which the individual acts may beperformed. The following detailed description is, therefore, not to beconstrued in a limiting sense. Wherever possible, the same or likereference numbers are used throughout the drawings to refer to the sameor like structural components or parts.

Certain DC-DC converters (e.g., step-down or buck converters) commonlyutilize a compensation filter or “feedback amplifier” for closed-loopregulation so that the feedback network gain and phase as a function offrequency ensure that the overall system with feedback remains stable.For example, certain buck converters include Type-III Switched CapacitorFilter (SCF) compensation to ensure that their stability, transientresponse and closed loop performance meets the requirements imposed bythe overall systems involved. Nevertheless, a significant problem withthese buck converters is that one or more sample and hold amplifier(SHA) stages are needed to operate the SCF circuit and prevent aliasingdistortion. Each SHA stage adds a phase lag of T/2 (where T is thesampling period of the SCF) to the feedback loop, which is highlyundesirable in such a closed loop system because the phase lag directlyand negatively impacts the stability, transient response and thus theclosed loop performance of the buck converter and system involved. Also,each SHA stage increases the footprint, power consumption and cost forthe dies on which the SCF compensation circuits are formed. Furthermore,the existing SCF compensation circuits generate a complex, highfrequency pole, which further degrades their closed loop performance andthus the stability and performance of the buck converters involved.Finally, this high frequency pole requires the utilization of highbandwidth amplification circuitry in the SCF compensation circuitsinvolved, which results in much higher power dissipation requirementsthan desired. Nevertheless, as described below, the present inventionresolves these and other, related problems with enhanced Type-III SCFcompensation in buck converters formed on integrated circuits, wafers,chips or dies.

FIG. 1 depicts a schematic circuit diagram of a switched capacitorfilter (SCF) compensation circuit 100, which can be utilized toimplement one exemplary embodiment of the present invention. In theexemplary embodiment shown, the SCF compensation circuit 100 includes a“delay-free” Type-III SCF circuit with a continuous-time integratorfront-end. A differential difference amplifier (DDA) with two pairs ofdifferential inputs is utilized in the SCF compensation circuit 100 torealize a type-III filter transfer function, which enables the implicitcascading of the transfer functions realized at the two differentialinput pairs of the DDA. Consequently, the embodiment depicted in FIG. 1can be utilized as a compact discrete-time filter, which eliminates theneed for SHA stages, high bandwidth amplification stages, and thecomplex, high frequency poles generated in the existing SCF compensationcircuits.

Specifically, referring to FIG. 1, the SCF compensation circuit 100receives a voltage feedback signal, V_(FB), at an input 102, which iscoupled to the first terminal of a resistor R₀ 103. In this embodiment,the voltage feedback signal, V_(FB), is coupled to the resistor R₀ 103from the output terminal of a voltage-controlled, switched-modepulse-width-modulation (PWM) buck converter. In a second embodiment, forexample, the voltage feedback signal, V_(FB), can be coupled to theresistor R₀ 103 from the output terminal of a switched-mode PWM boostconverter, or the output node of any other suitable DC-DC voltageconverter. In any event, the second terminal of the resistor R₀ 103 isconnected to the first terminal of a capacitor C₀ 104 and the invertinginput of an error amplifier (e.g., operational amplifier) 106. Thenon-inverting input of the error amplifier 106 is coupled to a referencevoltage signal, V_(REF) 105. The reference voltage signal, V_(REF) 105,which is coupled to the non-inverting input of the error amplifier 106,has a voltage level that indicates the target voltage level for theoutput voltage of the buck converter involved. The circuitry includingthe resistor R₀ 103, capacitor C₀ 104 and error amplifier 106 functionsas an integrator circuit 109, which provides an integrated voltagesignal V_(INTEG) at the output of the error amplifier 106 and the node108. Note that, for example, in a different aspect of this embodiment,the integrator circuit 109 can also be implemented by utilizing anOperational Transconductance Amplifier (OTA) loaded with a capacitor.

The SCF compensation circuit 100 also includes a DDA 110. The DDA 110includes two input pairs: (V₁₊, V¹⁻) and (V₂₊, V²⁻). The integratedvoltage (error) signal V_(INTEG) at the node 108 is coupled to the V₂₊terminal of the DDA 110. A common-mode voltage signal, V_(CM), (e.g.,circuit reference voltage which may be different from V_(REF) 105) iscoupled to the V₁₊ terminal of the DDA 110. The common-mode voltagesignal, V_(CM), which is a DC voltage and an AC ground, is also coupledto a first terminal of a second capacitor, C₂ 112. The common-modevoltage signal, V_(CM), functions as a bias point for the DDA 110 toensure that the DDA 110 operates as required As such, for this exemplaryembodiment, the common-mode voltage, V_(CM), can be selected to bemid-rail or (VDD−GND)/2 and can be treated as an AC ground. The secondterminal of the second capacitor C₂ 112 is coupled to the V¹⁻ terminalof the DDA 110, and the voltage feedback signal, V_(FB), is coupled tothe V²⁻ terminal of the DDA 110.

The second terminal of the second capacitor, C₂ 112, is also coupled toa first terminal of a third capacitor C₃ 116, a first terminal of afirst transistor (e.g., MOSFET) switch 118 a (Φ₂), and a second terminalof a second transistor (e.g., MOSFET) switch 118 b (Φ₁). The secondterminal of the first transistor switch 118 a is coupled to a firstterminal of a fourth (switching) capacitor, C₄ 120 a, 120 b and a firstterminal of a third transistor (e.g., MOSFET) switch 122 a (Φ₁). Thesecond terminal of the fourth capacitor C₄ 120 a, 120 b is coupled to afirst terminal of a fourth transistor (e.g., MOSFET) switch 122 b (Φ₂).The second terminals of the transistor switches 122 a, 122 b and thethird capacitor C₃ 116 are coupled to the output terminal of the DDA110, which provides an error or compensation voltage signal, V_(COMP),at the output node 114. In the exemplary embodiment shown in FIG. 1, theinput pair V₁₊ and V¹⁻ and the output of the DDA 110, V_(COMP)encompassed by the capacitors C₂ 112, C₃ 116, C₄ 120 a and 120 b, andswitches 118 a, 118 b, 122 a and 122 b function together to provide anegative feedback network. The compensation voltage signal, V_(COMP), atthe output of the DDA 110 is coupled to an input of the PWM controllerof a DC-DC converter (e.g., to the input of a PWM comparator of a buckconverter, as in the embodiment depicted in FIG. 4) to maintain theoutput voltage of the converter at a substantially constant value. Notethat, in this exemplary embodiment, the transistor switches 118 a, 118b, 122 a, 122 b, the third capacitor C₃ 116, the (dual) fourth capacitorC₄ 120 a, 120 b, and the DDA 110 are structured to provide a Type-IIISCF circuit 101.

In order to implement the Type-III SCF circuit 101 depicted in FIG. 1, avalid assumption can be made that the DDA 110 has an infinite gain. (Inaddition, since V_(CM) and V_(REF) are DC voltages, the common-modevoltage V_(CM)=V_(REF)=AC ground). Consequently, the followingrelationship can be derived:

V _(INTEG) −V _(FB)=0−V ₂  (1)

The integrated voltage signal, V_(INTEG), can be expressed as follows(assuming infinite gain for the error amplifier 106):

$\begin{matrix}{V_{INTEG} = {{- \frac{1}{{sR}_{0}C_{0}}} \times V_{FB}}} & (2)\end{matrix}$

Mathematically manipulating the voltage signals at the inputs of the DDA110 produces the following expressions:

$\begin{matrix}{{V_{INTEG} - V_{FB}} = {{\left( {{- \frac{1}{{sR}_{0}C_{0}}} - 1} \right) \times V_{FB}} = {{- \left( \frac{1 + {{sR}_{0}C_{0}}}{{sR}_{0}C_{0}} \right)} \times V_{FB}}}} & (3) \\\begin{matrix}{{\left( {V_{2} - 0} \right) \times {sC}_{2}} = {\left( {V_{COMP} - V_{2}} \right) \div \left( R_{{EQ}\; 4}||\frac{1}{{sC}_{3}} \right)}} \\{= {\left( {V_{COMP} - V_{2}} \right) \div \left( \frac{R_{{EQ}\; 4}}{1 + {{sC}_{3}R_{{EQ}\; 4}}} \right)}}\end{matrix} & (4) \\{{V_{2} \times \left( \frac{R_{{EQ}\; 4}}{1 + {{sC}_{3}R_{{EQ}\; 4}}} \right){sC}_{2}} = \left( {V_{COMP} - V_{2}} \right)} & (5) \\{{V_{2} \times \left\lbrack {1 + {\left( \frac{R_{{EQ}\; 4}}{1 + {{sC}_{3}R_{{EQ}\; 4}}} \right){sC}_{2}}} \right\rbrack} = V_{COMP}} & (6) \\{{\therefore V_{2}} = {V_{COMP} \times \frac{1 + {{sC}_{3}R_{{EQ}\; 4}}}{1 + {{sC}_{3}R_{{EQ}\; 4}} + {{sC}_{2}R_{{EQ}\; 4}}}}} & (7)\end{matrix}$

Substituting Equations (3) and (7) in Equation (1) produces thefollowing expressions:

$\begin{matrix}{{{- \left( \frac{1 + {{sR}_{0}C_{0}}}{{sR}_{0}C_{0}} \right)} \times V_{FB}} = {{- V_{COMP}} \times \frac{1 + {{sC}_{3}R_{{EQ}\; 4}}}{1 + {{sC}_{3}R_{{EQ}\; 4}} + {{sC}_{2}R_{{EQ}\; 4}}}}} & (8) \\{{\left( \frac{1 + {{sR}_{0}C_{0}}}{{sR}_{0}C_{0}} \right) \times \frac{1 + {{sC}_{3}R_{{EQ}\; 4}} + {{sC}_{2}R_{{EQ}\; 4}}}{1 + {{sC}_{3}R_{{EQ}\; 4}}}} = \frac{V_{COMP}}{V_{FB}}} & (9)\end{matrix}$

Note that, as indicated by Equation (9), the manipulation of thetransfer functions at the inputs of the DDA 110 produces two poles: onepole is placed at the origin to provide a high level of DC voltageregulation; and the second pole is placed at high frequency.Additionally, two real zeros are placed close to theinductance-capacitance (LC) double-pole frequency present involtage-mode control. Also note that the term R_(EQ4) in Equation (9)represents the resistor equivalent of the switched capacitor, C₄. Assuch, a bilinear transformation (BLT) can be utilized to convert thecontinuous-time filter (represented in the Laplace or “s” domain) into adiscrete-time filter (represented in the “z” domain), as describeddirectly below.

In order to obtain the discrete-time filter representation of the SCFcircuit 100, the BLT equation can be expressed as:

$\begin{matrix}{s = {\frac{2}{T} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}} & (10)\end{matrix}$

Where, T is the sampling time period of the SCF. In the exemplaryembodiment depicted in FIG. 1, the sampling period is assumed to beequal to one half of the clock period because double sampling isutilized. Thus, for the embodiment depicted in FIG. 1, the sampling timeperiod, T=T_(CLK)/2. Note that only the resistor equivalent, R_(EQ4), ofthe switching capacitor C₄, contributes to the discrete-time filteringfunction in Equation (9). As such, this discrete-time function is validfrom [0, ½T]. The remainder of Equation (9) is valid for all analogfrequency values from [0, ∞). However, by selecting the closed-loopcutoff frequency to be substantially smaller than 1/T, the highfrequency distortion has minimal impact on the overall transferfunction. Thus, Equation (7) can be rewritten in transfer function form:

$\begin{matrix}{\frac{V_{COMP}}{V_{2}} = \frac{1 + {\frac{C_{3}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}} + {\frac{C_{2}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}}{1 + {\frac{C_{3}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}}} & (11)\end{matrix}$

The complete frequency response of the transfer function is thenobtained by substituting the following in Equation (11):

z=e ^(jωT)  (12)

In summary, the SCF compensation circuit 101 depicted in FIG. 1 includesa DDA, which realizes a Type-III filter transfer function that enablesthe cascading of the two transfer functions realized at the differentialinput pairs of the DDA. Consequently, utilizing the embodiment depictedin FIG. 1 as a discrete-time filter, substantial benefits are derivedover those of the existing SCF compensation circuits, such aseliminating the need for the SHA stages and high amplifier bandwidthsrequired, reducing the footprint and power consumption requirements forthe dies produced, and enhancing the closed loop performance andstability of the DC-DC (e.g., buck) converters and overall systemsinvolved.

FIG. 2 depicts a schematic circuit diagram of a SCF compensation circuit200, which can be utilized to implement a second exemplary embodiment ofthe present invention. For example, the SCF compensation circuit 200 canbe utilized to provide Type-III SCF compensation for closed loopregulation in a buck converter. In the exemplary embodiment shown inFIG. 2, the SCF compensation circuit 200 includes a delay-free Type-IIISCF circuit 201 with a sampled-data, integrator front-end. As such, theSCF compensation circuit 200 shown in FIG. 2 is a fully-sampled, analogversion of the Type-III SCF compensation circuit 100 shown in FIG. 1.Merely by making the SCF sampling time period (T=T_(SW)/K) a fraction ofthe buck converter switching time period (T_(SW)), a Type-III filter isrealized that is fully-integrated into the buck converter, requires notrimming, and whose transfer function scales linearly with the switchingtime period T_(SW). Hence, the closed loop stability can theoreticallybe ensured for any value of T_(SW).

Specifically, the SCF compensation circuit 200 receives a voltagefeedback signal, V_(FB), (e.g., from the output node of a buckconverter) at an input node 202. The input node 202 is connected to theinput terminal of a sampled-data front-end circuit 230 (described indetail below). The output terminal of the sampled-data front-end circuit230 is coupled to a node 203, which is connected to the first terminalof a capacitor C₀ 204 and the inverting input of an error amplifier(e.g., operational amplifier) 206. The non-inverting input of the erroramplifier 206 is connected to receive a reference voltage signal,V_(REF) 205. The circuitry including the sampled-data front-end circuit230, capacitor C₀ 204 and error amplifier 206 functions as an integratorcircuit 209 to provide an integrated voltage signal V_(INTEG) at theoutput of the error amplifier 206 and the node 208. As such, and asdescribed in detail below, in this exemplary embodiment, the SCFcompensation circuit 200 includes a sampled-data, integrator front-endcircuit.

The integrated voltage signal V_(INTEG) at the node 208 is coupled tothe V₂₊ input of a DDA 210. The voltage feedback signal, V_(FB), iscoupled to the V²⁻ input of the DDA 210. The V₁₊ input of the DDA 210 iscoupled to a common-mode voltage signal, V_(CM) (e.g., circuit referencevoltage signal). The common-mode voltage signal, V_(CM), which is a DCvoltage and an AC ground, is also coupled to a first terminal of asecond capacitor, C₂ 212. As such, the common-mode voltage signal,V_(CM), functions as a bias point to ensure that the DDA 210 functionsas required. For this exemplary embodiment, the common-mode voltage,V_(CM), is selected to be mid-rail or V_(CM)=(VDD−GND)/2. The secondterminal of the second capacitor C₂ 212 is coupled to the V¹⁻ input ofthe DDA 210. The output of the DDA 210 provides a compensation voltagesignal, V_(COMP), at the output node 214. In this exemplary embodiment,the output node 214 is coupled to the DC-DC (buck) converter involved.

The second terminal of the second capacitor, C₂ 212, is also coupled toa first terminal of a third capacitor C₃ 216, a first terminal of afirst transistor (e.g., MOSFET) switch 218 a (Φ₂), and a second terminalof a second transistor (e.g., MOSFET) switch 218 b (Φ₁). The secondterminal of the first transistor switch 218 a is coupled to a firstterminal of a fourth (switching) capacitor, C₄ 220 a, 220 b and a firstterminal of a third transistor (e.g., MOSFET) switch 222 a (Φ₁). Thesecond terminal of the fourth capacitor C₄ 220 a, 220 b is coupled to afirst terminal of a fourth transistor (e.g., MOSFET) switch 222 b (Φ₂).The second terminals of the transistor switches 222 a, 222 b and thethird capacitor C₃ 216 are coupled to the output node 214. Thus, in thisexemplary embodiment, the transistor switches 218 a, 218 b, 222 a, 222b, the (switching) fourth capacitor C₄ 220 and the DDA 210 functiontogether to provide a Type-III SCF 201.

In this embodiment, the sampled-data, front-end circuit 230 receives thefeedback voltage signal, V_(FB), at a first terminal of a fifthtransistor (e.g., MOSFET) switch 224 a (Φ₁), and a first terminal of asixth transistor (e.g., MOSFET) switch 224 b (Φ₁). The second terminalof the fifth transistor switch 224 a is coupled to a first terminal of aswitching capacitor, C₁ 226 a, 226 b and a first terminal of a seventhtransistor (e.g., MOSFET) switch 228 a (Φ₂). The second terminal of theswitching (fifth) capacitor C₁ 226 a, 226 b is coupled to the secondterminal of the sixth transistor switch 224 b and a first terminal of aneighth transistor (e.g., MOSFET) switch 228 b (Φ₂). The second terminalof the eighth transistor switch 228 b is coupled to the second terminalof the seventh transistor switch 228 a and the node 203. Thus, theType-III SCF 200 includes a sampled-data circuit (230) and integratorcircuit (209) front-end.

In this exemplary embodiment, both of the switching capacitors, C₁ 226and C₄ 220, can be implemented as equivalent resistors R_(EQ1) andR_(EQ4), respectively, in the discrete-time domain. Therefore, assumingthat Equations (1)-(8) above can also apply for this embodiment,Equation (9) can be rewritten and thus expressed as follows:

$\begin{matrix}{\frac{V_{COMP}}{V_{FB}} = {\left( \frac{1 + {{sR}_{{EQ}\; 1}C_{0}}}{{sR}_{{EQ}\; 1}C_{0}} \right) \times \frac{1 + {{sC}_{3}R_{{EQ}\; 4}} + {{sC}_{2}R_{{EQ}\; 4}}}{1 + {{sC}_{3}R_{{EQ}\; 4}}}}} & (13)\end{matrix}$

As such, for this embodiment, in the discrete time domain, Equation (13)can be expressed as follows:

$\begin{matrix}{\frac{V_{COMP}}{V_{FB}} = {\left( \frac{1 + {\frac{C_{0}}{C_{1}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}}{\frac{C_{0}}{C_{1}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}} \right) \times \frac{1 + {\frac{C_{3}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}} + {\frac{C_{2}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}}{1 + {\frac{C_{3}}{C_{4}} \times \frac{1 - z^{- 1}}{1 + z^{- 1}}}}}} & (14)\end{matrix}$

Again, the complete frequency response of this transfer function can beobtained by substituting Equation (12) above in Equation (14).

In summary, the Type-III SCF compensation circuit 200 depicted in theembodiment of FIG. 2 realizes all of the enhancements described abovewith respect to the embodiment depicted in FIG. 1. Additionally, thesampled-data front end circuit 230 in the embodiment depicted in FIG. 2can be utilized to directly sample the feedback voltage at the output ofthe DC-DC (buck) converter involved. This function can be implementedespecially where the buck converter's ripple voltage is small (andespecially when ceramic output capacitors are utilized). However, theimplicit low-pass filtering of the switching capacitor integrator inthis embodiment prevents aliasing distortion (and thus eliminates theneed for an Anti-Aliasing Filter) even if the ripple voltage is high.

FIG. 3 depicts a flow diagram of a method 300, which can be utilized toimplement Type-III SCF compensation for a DC-DC converter, in accordancewith one exemplary embodiment of the present invention. In thisembodiment, the method 300 is utilized to implement SCF compensation fora buck converter. However, in other embodiments, the method 300 can alsobe utilized to implement SCF compensation for other suitable types ofvoltage converters in which SCF compensation is desired. Referring toFIGS. 1 and 3, the exemplary method 300 begins by integrating an errorvoltage signal generated at the output node 108 of the integrator 109(302). The integrated error voltage signal, which is derived from thefeedback voltage, V_(FB), received at the input terminal 102, is coupledto the V₂₊ differential input of the DDA 110. The SCF 101 filters avoltage signal (304) associated with the common-mode voltage, V_(CM),and thereby generates a filtered voltage signal at the V¹⁻ differentialinput of the DDA 110. The DDA 110 amplifies the integrated error voltagesignal and the filtered voltage signal (306), and generates at itsoutput (and the output node coupled to the buck converter) 114 acompensation voltage signal in response to amplifying the integratedvoltage signal and the filtered voltage signal at the respective inputsto the two differential input pairs (308). More precisely, thecompensation voltage signal at the output 114 of the DDA 110 is thedifference between the voltage signals received at the two differentialinput pairs. As such, the DDA 110 functions implicitly to cascade thetransfer functions of the voltage signals realized at the twodifferential input pairs.

FIG. 4 depicts a schematic circuit diagram of a DC-DC converter 400,which can be utilized to implement one exemplary embodiment of thepresent invention. In the exemplary embodiment shown, the DC-DCconverter 400 is a voltage-mode controlled buck converter with Type-IIISCF compensation. In a second embodiment, the DC-DC converter 400 can bea boost converter or a buck-boost converter with Type-III SCFcompensation. Referring to the exemplary embodiment depicted in FIG. 4,the buck converter 400 includes a power circuit 402 and a voltage-modePWM controller circuit 404. In this exemplary embodiment, the powercircuit 402 and controller circuit 404 are formed on separate integratedcircuits, wafers, chips or dies. In a second embodiment, the powercircuit 402 and controller circuit 404 can be formed on a singleintegrated circuit, wafer, chip or die.

In the embodiment depicted in FIG. 4, the power circuit 402 includes ahigh side driver amplifier 406 and a low side driver amplifier 408. Theinput terminals of the driver amplifiers 406, 408 are coupled to theoutput of the controller circuit 404. The output terminals of the highside driver amplifier 406 and low side driver amplifier 408 are coupled,respectively, to the control terminals of a high side switching (e.g.,NMOS) transistor 410 and low side switching (e.g., NMOS) transistor 412.The switching voltage, V_(SW), at the output node between the switchingtransistors 410, 412 is coupled to and developed across the resistor,R_(L) 414. The voltage developed across the resistor, R_(L) 414 iscoupled to the inductor, L 416, which in turn generates the inductorcurrent, I_(L). The output voltage of the power circuit 402 is developedat the output node, B_(OUT) 418, and filtered by the RC network 420,422.

The voltage, V_(OUT), at the output node 418 of the power circuit 402 iscoupled to the feedback voltage input, V_(FB) in the SCF compensationcircuit 424. For example, referring to FIG. 1, the voltage V_(OUT) canbe coupled to the feedback voltage input, V_(FB) 102 depicted in thatembodiment, or alternatively, referring to FIG. 2, the voltage V_(OUT)can be coupled to the feedback voltage input, V_(FB) 202 in the SCFcompensation circuit 200 depicted in that embodiment. The compensationvoltage signal, V_(COMP), at the output of the SCF compensation circuit424 is coupled to the non-inverting input terminal of a PWM comparator426. For example, referring to FIG. 1, the voltage V_(COMP) can becoupled to the power circuit 402 from the output terminal 114 in the SCFcompensation circuit 100 depicted in that embodiment, or alternatively,referring to FIG. 2, the voltage V_(COMP) can be coupled to the powercircuit 402 from the output terminal 214 in the SCF compensation circuit200 depicted in that embodiment. The voltage-mode PWM controller circuit404 also includes a clock circuit 428, which generates a clock (timing)pulse. The clock pulse is coupled to a sawtooth generator circuit 430,which generates a sawtooth voltage signal, V_(SAW) that is coupled tothe inverting input terminal of the PWM comparator 426. The PWM voltagesignal, V_(PWM) thus generated at the output of the PWM comparator 426and the output terminal of the voltage-mode PWM controller 404 iscoupled to the respective input terminals of the high side and low sidedriver amplifiers 406, 408 in the power circuit 402.

FIG. 5 depicts a schematic block diagram of an electronic system 500,which can be utilized to implement one exemplary embodiment of thepresent invention. In the exemplary embodiment shown, electronic system500 includes a power subsystem 502, a digital processor unit 504, and aperipheral subsystem 506. For example, the digital processor unit 504can be a microprocessor or microcontroller and the like. The peripheralsubsystem 506 includes a memory unit 508 for storing the data processedby the digital processor unit 504, and an input/output (I/O) unit 510for transmitting and receiving the data to/from the memory unit 508 andthe digital processor unit 504. In the exemplary embodiment depicted inFIG. 5, the power subsystem 502 includes a DC-DC converter 512, and anSCF compensation circuit 514 for closed loop regulation of the converter512. For example, the DC-DC converter 512 can be implemented utilizingthe DC-DC (buck) converter 400 depicted in FIG. 4, and the SCFcompensation circuit 514 can be the SCF compensation circuit 424depicted in FIG. 4. The DC-DC converter 512 and power subsystem 502provide a regulated voltage via line 516 to power the electroniccomponents in the digital processor unit 504 and peripheral subsystem506. In the exemplary embodiment shown in FIG. 5, the SCF compensationcircuit 514 can be implemented, for example, utilizing the Type-III SCFcompensation circuit 100 depicted in FIG. 1, or alternatively, utilizingthe fully sampled, Type-III SCF compensation circuit 200 depicted inFIG. 2. In one or more embodiments, the components of the electronicsystem 500 can be implemented in one or more integrated circuits,wafers, chips or dies.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiments shown. Therefore, it ismanifestly intended that the present application be limited only by theclaims and the equivalents thereof.

What is claimed is:
 1. A method of compensation for a DC-DC converter,the method comprising: integrating an error voltage signal; filtering avoltage signal; amplifying the integrated error voltage signal and thefiltered voltage signal; and generating a compensation voltage signalresponsive to the amplifying the integrated error voltage signal and thefiltered voltage signal.
 2. The method of claim 1, wherein theamplifying comprises amplifying a difference between the integratederror voltage signal and the filtered voltage signal.
 3. The method ofclaim 1, wherein the filtering comprises switched-capacitor filteringthe voltage signal.
 4. The method of claim 1, further comprisingreceiving a feedback voltage signal and generating the error voltagesignal responsive to the feedback voltage signal.
 5. The method of claim1, wherein the amplifying comprises generating an amplified signalassociated with a first transfer function for the integrated errorvoltage signal and a second transfer function for the filtered voltagesignal.
 6. The method of claim 1, further comprising generating apulse-width modulation (PWM) voltage signal responsive to thecompensation voltage signal.
 7. A compensation circuit, comprising: anintegrator circuit configured to receive and integrate a first voltagesignal; a differential difference amplifier circuit coupled to theintegrator circuit and configured to generate a first filter transferfunction associated with the integrated first voltage signal; and aswitched capacitor filter circuit coupled to the differential differenceamplifier circuit and configured to generate a second filter transferfunction, wherein the differential difference amplifier is furtherconfigured to output a second voltage signal responsive to the firstfilter transfer function and the second filter transfer function.
 8. Thecompensation circuit of claim 7, wherein the compensation circuitcomprises a type-III switched capacitor filter compensation circuit fora DC-DC converter.
 9. The compensation circuit of claim 7, wherein theintegrator circuit comprises a continuous-time integrator front-endcircuit.
 10. The compensation circuit of claim 7, wherein the integratorcircuit comprises a switched capacitor integrator circuit.
 11. Thecompensation circuit of claim 7, wherein the switched capacitor filtercircuit comprises a type-III switched capacitor filter circuit.
 12. Thecompensation circuit of claim 7, wherein the differential differenceamplifier includes a first input configured to receive the integratedfirst voltage signal, a second input configured to receive the firstvoltage signal, a third input configured to receive a common-modevoltage signal, and a fourth input configured to receive a filteredvoltage signal associated with the common-mode voltage signal.
 13. Thecompensation circuit of claim 7, wherein the differential differenceamplifier circuit includes two pairs of differential inputs.
 14. Thecompensation circuit of claim 7, wherein the differential differenceamplifier circuit is configured to realize a type-III filter transferfunction that enables an implicit cascading of transfer functionsreceived at two pairs of differential inputs of the differentialdifference amplifier.
 15. A DC-DC voltage converter, comprising: a powercircuit; and a controller circuit coupled to the power circuit, thecontroller circuit including a compensation circuit comprising: anintegrator circuit configured to receive an output voltage from theDC-DC voltage converter and integrate the output voltage signal; adifferential difference amplifier circuit coupled to the integratorcircuit and configured to generate a first filter transfer functionassociated with the integrated output voltage signal; and a switchedcapacitor filter circuit coupled to the differential differenceamplifier circuit and configured to generate a second filter transferfunction, wherein the differential difference amplifier is furtherconfigured to generate a compensation voltage signal for the DC-DCvoltage converter responsive to the first filter transfer function andthe second filter transfer function.
 16. The DC-DC voltage converter ofclaim 15, wherein the DC-DC voltage converter comprises a switched modePWM voltage converter.
 17. The DC-DC voltage converter of claim 15,wherein the DC-DC voltage converter comprises a buck converter orstep-down voltage converter.
 18. An electronic system, comprising: adigital processor; a peripheral subsystem coupled to the digitalprocessor; and a power subsystem coupled to the digital processor andcircuit components of the peripheral subsystem and configured togenerate an output voltage to power the digital processor and thecircuit components of the peripheral subsystem, wherein the powersubsystem includes a DC-DC converter configured to regulate the outputvoltage of the power subsystem, and the DC-DC converter includes aswitched capacitor filter compensation circuit comprising: an integratorcircuit configured to receive and integrate a difference of the outputvoltage and a reference voltage; a differential difference amplifiercircuit coupled to an output of the integrator circuit and configured togenerate a first filter transfer function; and a switched capacitorfilter circuit coupled to the differential difference amplifier circuitand configured to generate a second filter transfer function, whereinthe differential difference amplifier is further configured to output acompensation voltage signal for the DC-DC converter responsive to thefirst filter transfer function and the second filter transfer function.19. The electronic system of claim 18, wherein the DC-DC convertercomprises a buck converter.
 20. The electronic system of claim 18,wherein the switched capacitor filter compensation circuit and the powersubsystem are formed on one or more integrated circuits, wafers, chipsor dies.